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A 700-V device in high-voltage power ICs with low on-state resistance and enhanced SOA
Journal article   Peer reviewed

A 700-V device in high-voltage power ICs with low on-state resistance and enhanced SOA

Fu-Jen Yang, Jeng Gong, Ru-Yi Su, Ker-Hsiao Huo, Chun-Lin Tsai, Chih-Chang Cheng, Ruey-Hsin Liou, Hsiao-Chin Tuan and Chih-Fang Huang
IEEE Transactions on Electron Devices, Vol.60(9), pp.2847-2853
2013

Abstract

Breakdown voltage (BV) electric field high voltage laterally diffused metal-oxide-semiconductor (LDMOS) p-body (PB) power device RONsp reduce surface field (RESURF) safe operating area (SOA) Triple RESURF
This paper presents a 700-V high-voltage laterally diffused metal-oxide-semiconductor (LDMOS) field-effect transistor with a p-body-Extension reduce surface field (RESURF) structure. Experimental results demonstrate that the low ON resistance and breakdown voltage (BV)-R ON,sp figure of merit approach the ideal Baliga's power law, in addition, breaks the quasi-saturation limitation with enhanced device safe operating area (SOA). The optimal charge balance and geometrical design to achieve the lowest specific ON resistance (R ON,sp ) with the desired maximum high BV are displayed and discussed by simulations and experimental results. The 2-D simulations confirmed that, compared with conventional triple-RESURF structures, the presented device provides a fourfold reduction in the surface electric field on the source side and a 32% improvement in blocking voltage. The specific ON resistance demonstrates superior 40% lower performance than published Junction Isolation LDMOS device families. In addition, its twofold increase in SOA extension can improve the performance of circuit designs for switching power supply applications. © 1963-2012 IEEE.

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