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A Balunless Frequency Multiplier With Differential Output by Current Flow Manipulation
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A Balunless Frequency Multiplier With Differential Output by Current Flow Manipulation

Chun-Hsing LiWei-Min Wu
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 卷.26(7), 頁碼.1391-1402
07/2018

摘要

Balunless CMOS differential output frequency doubler (FD) frequency multiplier (FM) low power Software Hardware and Architecture Electrical and Electronic Engineering
A balunless frequency doubler (FD) architecture which can provide differential output without any additional balun required is proposed in this paper. The architecture manipulates the desired second-harmonic currents around the doubler core by a multifunction network to avoid any leakage current path from the output current loop. Therefore, the output currents extracted from the same current loop can have the same amplitude and phase. As the output currents flow into and out of the same loads, respectively, the induced output voltages can be perfectly differential without needing to add a balun. A 60-GHz FD realized in a 90-nm CMOS technology is designed to verify the proposed FD architecture. The measured amplitude and phase imbalances of the differential output are only 0.2 dB and 0.5°, respectively, while providing -5.5-dB conversion gain at an output frequency of 60 GHz. The proposed FD only consumes 15.9 mW from a 1-V supply. The proposed doubler architecture can be theoretically extended to realize a frequency multiplier with a multiplication factor larger than 2.

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