摘要
This paper presents a calibration-free 12-bit 50-MS/s full-analog SAR analog-to-digital (A-to-D) converter (ADC) in 40-nm CMOS, which integrates the functions of comparator, SAR logic, and digital-to-analog converter (DAC) switches into multiple feedback zero-crossing detectors (FB-ZCDs). By eliminating all the digital circuits, the full-analog bit conversions operate with the asynchronous amplification-to-regeneration (A-to-R) operation that highly relaxes the requirements of the analog circuits and reference generator. This paper is implemented without any calibration, where the non-ideal effects (offset mismatch, insufficient residue, and noise) are mitigated and eliminated with the proposed techniques as follows. The offset mismatches among the FB-ZCDs are covered by the redundancies of the sub-radix DAC arrangement in the coarse ADC. The bottom-plate coupling compensators (BPCCs) are proposed to correct the consecutive SAR decision errors as quantizing the insufficient residue. The shared FB-ZCD with capacitor coupling decision (CCD) network is developed to obtain the identical offset in the fine ADC. Amplification extension (AE) technique is proposed to enhance the precision of the shared FB-ZCD by reconfiguring as a complementary inverter-based amplifier with the extended amplification period to enhance the output SNR. This paper occupies an active area of 0.01 mm 2 and achieves the Nyquist-rate signal-to-noise-and-distortion ratio (SNDR), spurious-free dynamic range (SFDR), Walden figure-of-merit (FoM W ), and Schreier FoM (FoM S ) of 64.1, 75.6 dB, 5.3 fJ/conversion step, and 172.8 dB, respectively.