摘要
This paper presents a calibration-free 13-bit 10-MS/s full-analog successive-approximation-register analog-to-digital converter (SAR ADC) in 40-nm CMOS, which fully utilizes the timing and power budgets in a bit-conversion cycle by eliminating the digital circuits entirely. Continuous-time feedforward cascaded (CTFC) op-amps are proposed to enhance the residue power without the necessity of high-precision quantizers. As opposed to the residue amplifiers (RAs) in multi-step/pipelined ADCs, the CTFC op-amps in the open-loop configuration are implemented with the relaxing gain-bandwidth product (GBW) and without the limitations of accurate gain, precise settling, and voltage swing. Inverter-based regenerative-amplifier (IRA)-based zero-crossing detectors (ZCDs) with self-triggered amplification-to-regeneration (A-to-R) operation are developed to perform serial full-analog SAR bit conversions. The stability in multiple negative feedback (NFB) loops formed by the CTFC op-amps and ZCDs is analyzed and confirmed. The input-referred noise (IRN) and input-referred offset (IRO) in each bit conversion are suppressed by the CTFC op-amps and tolerated by the digital-to-analog converter (DAC) radix and sub-ADC arrangements. The LSB repeating is adopted to entirely cancel out the suppressed IRO mismatches among the bit conversions in the fine ADC. This work occupies an active area of 0.013 mm 2 and achieves the Nyquist-rate signal-to-noise-and-distortion ratio (SNDR), spurious-free dynamic range (SFDR), Walden figure-of-merit (FoMw), and Schreier FoM (FoMS) of 67.6 dB, 77.2 dB, 3.3 fJ/conversion-step, and 176.5 dB, respectively.