摘要
This paper presents a comprehensive study of the impact of the silicon gate structure on the suppression of boron penetration in p + -gate devices. The characteristics and reliability for different gate structures (poly-Si, α-Si, poly-Si/poly-Si poly-Si/α-Si, α-Si/poly-Si, and α-Si/α-Si) in p+ polygate PMOS devices are investigated in detail. The suppression of boron penetration by the nitrided gate oxide is also discussed. The comparison is based on flatband voltage shift as well as the value of charge to breakdown. Results show that the effect of boron diffusion through the thin gate oxide in p + polygate PMOS devices can be significantly suppressed by employing the as-deposited amorphous silicon gate. Stacked structures can also be employed to suppress boron penetration at the expense of higher polygate gate resistance. The single layer as-deposited amorphous silicon is a suitable silicon gate material in the p + -gate PMOS device for future dual-gate CMOS process. In addition, by employing a long time annealing at 600° C prior to p+ gate ion implantation and activation, further improvements in suppression of boron penetration, polygate resistance, and gate oxide reliability can be achieved for the as-deposited amorphous-Si gate. Modifying the silicon gate structure instead of the gate dielectrics is an effective approach to suppress the boron penetration effect. © 1995 IEEE