摘要
Reducing the number of AND gates in logic networks benefits the applications in cryptography, security, and quantum computing. This work proposes a don&null approach to reduce the number of AND gates further in the well-optimized network. Furthermore, this work also proposes an enhanced synthesis flow by integrating our approach with the state-of-the-art. The experimental results show that our approach can further reduce up to 25% of the number of AND gates in the network. For the experiments about the enhanced synthesis flow, we achieve a speedup of almost 10X on average for the cryptography benchmarks while having competitive results as compared to the flow in the state-of-the-art.