摘要
This paper presents an analog-to-digital (A-to-D) conversion algorithm to break through the speed limitation of the analog-to-digital converters in advanced technology. The proposed A-to-D conversion algorithm utilizes the benefits of the speed-up techniques of sub-radix and multi-bit per cycle. We model the V in -V q transfer curves into linear equations with hardware-like parameters for in-depth analysis. The design constraints, guidelines, tradeoffs, and figure of merit (FoM) are provided for architecture optimization.