摘要
In this letter, a compact and very low power passive/active hybrid equalizer is presented. By sharing the loading of high frequency peaking with the active equalizing stage, the passive filtering stage at the input can reduce the power consumption significantly. To achieve a small area while maintaining high performance, the 3-D inductor and active inductor techniques are also incorporated. Implemented in a standard 90 nm CMOS process, the proposed equalizer only consumes 10.8 mW and occupies a core chip area of 0.017 ${m mm} 2 . The equalization function up to 22 Gb/s was successfully demonstrated with a gain of 10 dB at around 11 GHz for the data transmitted through a 180 cm coaxial cable line.