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A New High Density 3D Stackable Via RRAM for Computing-in-Memory SOC Applications
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A New High Density 3D Stackable Via RRAM for Computing-in-Memory SOC Applications

Siao-Ping Sing, Ya-Ching Wang, Wei-Hwa Lin, Yue-Der Chih, Yih Wang, Ya-Chin King 和 Chrong Jung Lin
IEEE Transactions on Electron Devices
2024
DOI: https://doi.org/10.1109/TED.2024.3367661

摘要

Artificial synapse CMOS logic Common Information Model (computing) computing-in-memory (CIM) Latches Layout Logic gates multiply–accumulate (MAC) neural network (NN) Resistance resistive random access memory (RRAM) Three-dimensional displays Voltage Electronic Optical and Magnetic Materials Electrical and Electronic Engineering
A novel 3D stackable Via resistive random access memory (RRAM) latch and Via RRAM logic gates implemented in 16-nm FinFET logic process for computing-in-memory (CIM) applications are proposed. Via RRAM latch array can provide more than 60 Mb/mm2 of latch storage density to achieve stable full-swing high-speed output. By simplifying the readout circuit, latch array allows flexible configuration in advanced SOC. Three-Dimensional Via RRAM logic gates compute the stored data internally. The features show a promising way to reduce the von Neumann bottleneck.

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