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A RRAM Integrated 4T SRAM with Self-Inhibit Resistive Switching Load by Pure CMOS Logic Process
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A RRAM Integrated 4T SRAM with Self-Inhibit Resistive Switching Load by Pure CMOS Logic Process

Meng-Yin Hsu, Chu-Feng Liao, Yi-Hong Shih, Chrong Jung LinYa-Chin King
Nanoscale Research Letters, 卷.12, 418
2017

摘要

CMOS logic process Logic non-volatile memory Resistive random access memory Static random access memory Materials Science (all) Condensed Matter Physics
This paper reports a novel full logic compatible 4T2R non-volatile static random access memory (nv-SRAM) featuring its self-inhibit data storing mechanism for in low-power/high-speed SRAM application. With compact cell area and full logic compatibility, this new nv-SRAM incorporates two STI-ReRAMs embedded inside the 4T SRAM. Data can be read/write through a cross-couple volatile structure for maintaining fast accessing speed. Data can be non-volatilely stored in new SRAM cell through a unique self-inhibit operation onto the resistive random access memory (RRAM) load, achieving zero static power during data hold.

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https://doi.org/10.1186/s11671-017-2191-9檢視
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