摘要
A space-filling clock tree is presented, which takes an advantage of LC resonant clocking, to obtain a uniform phase and amplitude multiply-by-3 clock from a unique Sierpinski-coupled ring oscillator (SCRO) array. The three-stage interleaved SCROs resemble the Sierpinski triangle, and are synchronized with a common frequency to all. The SCRO further provides an aligned output phase relationship to reduce skew. The triangle clock grid with a side length of 3.2 mm is filled by a space-filling clock tree. The 3-D stacked transformers at the tree endpoints extract the third harmonic of the SCRO array oscillation and scale the voltage amplitude of the extracted clock. The transformers also perform a built-in bandpass filtering function to remove injected noise. An experimental prototype integrated in a 90-nm CMOS operates at 2.85-4.3 GHz and consumes 19.2-49 mW under 0.7-1 V supply voltages. With 300-mV added supply noise, jitter was measured as 3.4 ps (rms) and 17.7 ps (pp). The measured results reveal substantial improvements in both power and jitter from this approach.