Abstract
In this corresondence, a new serial-in serial-out systolic array is presented for performing the element inversion in GF(2m) with the standard basis representation. The architecture is highly regular, modular, nearest neighbor connected, and thus well suited to VLSI implementation. It has a latency of 7?n-3 clock cycles and a throughput rate of one result per 2m-l clock cycles. This speed performance is much better than those of the previous implementations. Without change in hardware design, the proposed inversion array can be directly used for computing the division in GF(2m). © 1993 IEEE