A hierarchical test methodology for systems on chip

期刊文章

Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Pin Su, Cheng-Wen Wu, Chuang Cheng, Shao-I Chen, Chi-Yi Hwang 和 Hsiao-Ping Lin

IEEE Micro, 卷.22(5), 頁碼.69-81

09/2002

摘要

Computer Graphics and Computer-Aided Design

Hardware and Architecture

Software

1 檢視次數

題名: A hierarchical test methodology for systems on chip
翻譯題名: A hierarchical test methodology for systems on chip
創作者：: Jin-Fu Li (作者) - National Central University
Hsin-Jung Huang (作者) - National Tsing Hua University
Jeng-Bin Chen (作者) - National Tsing Hua University
Chih-Pin Su (作者) - National Tsing Hua University
Cheng-Wen Wu (作者) - National Tsing Hua University
Chuang Cheng (作者) - Faraday Technology (United States)
Shao-I Chen (作者) - Faraday Technology (United States)
Chi-Yi Hwang (作者) - Faraday Technology (United States)
Hsiao-Ping Lin (作者) - Faraday Technology (United States)
學術資源類型: 期刊文章
出版日期: 09/2002
出版資訊: IEEE Micro, 卷.22(5), 頁碼.69-81
語言: 英語