Abstract
Space-time trellis code (STTC) has been widely applied to coded multiple-input multiple-output (MIMO) systems because of its gains in coding and diversity; however, its great decoding complexity makes it less promising in chip realization compared to the space-time block code (STBC). The complexity of STTC decoding lies in the branch metric calculation in the Viterbi algorithm and increases significantly along with the number of antennas and the modulation order. Consequently, a low-complexity algorithm to mitigate the computational burden is proposed. The results show that more than 70%, 78%, and 83% of the computational complexity is reduced for 2 × 2, 3 × 3, and 4 × 4 MIMO configurations, respectively. Based on the proposed algorithm, a reconfigurable MISO STTC Viterbi decoder is designed and implemented using 0.18 μm 1P6M CMOS technology. The decoder achieves 11.14 Mbps, 8.36 Mbps, and 5.75 Mbps for 4-PSK, 8-PSK, and 16-QAM modulations, respectively. © 2006 IEEE.