Abstract
This brief presents a new fast algorithm along with its systolic array implementation for computing the JV-point discrete cosine transform (DCT), where JV is a power of two. The architecture requires log2./V multipliers and can evaluate one complete JV-point DCT (i.e., N transform samples) every N clock cycles. Due to the features of regularity and modularity, it is well suited to VLSI implementation. As compared to existing systolic DCT designs with the same throughput performance, the proposed one involves much less hardware complexity. © 1997 IEEE.