Abstract
Testing path delay faults (PDFs) in VLSI circuits is
becoming an important issue as we enter the deep submicron
age. However, it is difficult in general 1 since the
number of faults normally is very large and most faults
are hard to sensitize. To make delay fault testing and
test synthesis easier, we propose a probabilistic PDF
model. We investigate probability density functions for
wire and path, delay size to model the fault effect in the
circuit under. test. In our approach, delay fault size
is assumed to be randomly distributed. An analytical
model is proposed to evaluate the PDF coverage. We
show that the fault size of the undetected paths can be
greatly reduced if these paths are conjoined with other
detected paths. Therefore, by our approach, path selection
and synthesis of PDF testable circuits can be done
more accurately. Also, given a test set, fault coverage
can be predicted by calculating the mean delay of the
paths.