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A programmable BIST core for embedded DRAM
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A programmable BIST core for embedded DRAM

Chih-Tsun Huang, Jing-Reng Huang, Chi-Feng Wu, Cheng-Wen Wu 和 Tsin-Yuan Chang
IEEE Design and Test of Computers, 卷.16(1), 頁碼.59-69
01/1999
DOI: https://doi.org/10.1109/54.748806

摘要

Software Hardware and Architecture Electrical and Electronic Engineering
The programmable BIST design presented here supports various test modes using a simple controller. With the March C - algorithm, the BIST circuit's overhead is under 1.3% for a 1-Mbit DRAM and under 0.3% for a 16-Mbit DRAM. © 1999 IEEE.

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