Abstract
In this paper, we present a 2.56/3.2Gbps 16/20:1 SERDES circuit for high speed networking. To achieve high speed, low area and low-jitter requirements, we propose the quarter-rate SERDES architecture, true single phase clock (TSPC) circuit, and LC-VCO based PLL. This SERDES uses the quarter-rate architecture to reduce the high frequency clock requirement. The shift register and multiple phase sampling structures are adopted to achieve the 16/20:1 serializer and 1:16/20 deserializer. We also propose an area-saving RF device for the SERDES design. The area-saving RF device has almost the same speed and jitter performance as the original RF device but only consumes one half of the area. The grounded coplanar waveguide (GCPW) type transmission line is also employed to reduce the clock tree skew within 1ps in the SERDES. In measurement, this SERDES can operate up to 5.12Gbps independent of the PLL. Fabricated in 0.18μm CMOS process, the 2.49mmx2.49mm SERDES consumes 250mW at 3.2Gbps data rate.