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A sub-0.3 v area-efficient l-shaped 7t sram with read bitline swing expansion schemes based on boosted read-bitline, asymmetric-V$ \\\\\\\\\\\\\\\\ TH read-port, and offset cell vdd biasing techniques
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A sub-0.3 v area-efficient l-shaped 7t sram with read bitline swing expansion schemes based on boosted read-bitline, asymmetric-V$ \\\\\\\\\\\\\\\\ TH read-port, and offset cell vdd biasing techniques

Meng-Fan Chang, Ming-Pin Chen, Lai-Fu Chen, Shu-Meng Yang, Yao-Jen Kuo, Jui-Jen Wu, Hsiu-Yun Su, Yuan-Hua Chu, Wen-Ching Wu, Tzu-Yi Yang, …
IEEE Journal of Solid-State Circuits, Vol.48(10), pp.2558-2569
2013
DOI: https://doi.org/10.1109/JSSC.2013.2273835

Abstract

Bit-line swing hot carrier injection low voltage read-port SRAM Electrical and Electronic Engineering
In previous SRAM designs, reducing minimum operating voltage (VDDmin) inevitably resulted in devices with a large cell area (A). This work proposes an L-shaped 7T cell (L7T) and read-bitline (RBL) swing expansion scheme (RBL-EXPD) to minimize A$ast$ VDDmin for low-voltage applications. This L7T features an area-efficient cell layout and a read-disturb free decoupled 1T read port (RP) capable of providing a wide space for write margin improvement. The RBL-EXPD employs (1) boosted RBL (BRBL), (2) 1T-RP with asymmetric- V$ m TH , (AV-1TRP) and (3) offset cell-VDD biasing (OFS-CVDD) to expand RBL swing in both the upward and downward directions securing both 'High' and 'Low' sensing margins. A 65 nm 256-row 32 Kb L7T SRAM macro-fabricated using BRBL and AVTH-RP achieved a 260 mV VDDmin. The resulting A$ast$VDDmin is ~50% lower than that of conventional 8T SRAM devices. © 2013 IEEE.

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