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A systematic approach to memory test time reduction
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A systematic approach to memory test time reduction

Jen-Chieh Yeh, Shuo-Fen Kuo, Chao-Hsun Chen 和 Cheng-Wen Wu
IEEE Design and Test of Computers, 卷.25(6), 頁碼.560-570
2008
DOI: https://doi.org/10.1109/MDT.2008.152

摘要

Algorithm design and analysis Flash memory Heuristic algorithms Memory management Random access memory Semiconductor memory Timing Software Hardware and Architecture Electrical and Electronic Engineering
This article describes a method for reducing overall memory test time without sacrificing fault coverage. Key to this method is a test time reduction tool that helps remove redundant test items from the test flow, merge existing test patterns, and develop efficient new test patterns. © 2008 IEEE.

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