摘要
Double exposure alternating phase-shift mask (alt-PSM) technology with ArF (193 nm) exposure was used in the 0.1 μm technology node for patterning logic devices with polysilicon gates (polygate) ranging from 110 nm to 60 nm. A dual-trench mask fabrication process was developed in-house at TSMC, and controls for phase accuracy and intensity balance were established. Optical proximity correction (OPC) was performed on both binary masks and alt-PSM. Interactions between the binary and the PSM exposures were taking in to accounted during the correction. Using Model based OPC (MOPC) and a single calibrated resist model, the critical dimension (CD) linearity can be ideally matched to the designed CD for duty ratio >= 1:1.5 for polygate CD of 100 nm. CD variations for isolated and dense patterns with differing shifter width and height can be controlled within 5 nm for shifter width and height is larger than 200 nm and 250 nm, respectively. With this newly developed alt-PSM technology, 100 nm polygate logic product has been implemented exhibiting an enlarged DOF, good resist line edge roughness (LER), and CD uniformity (CDU).