摘要
Adiabatic quantum-flux parametron (AQFP) is a superconducting technology with extremely low power consumption compared to traditional CMOS structures. Since AQFP logic gates are all clocked by AC current, extra buffer cells are required to balance the length of data paths. Furthermore, since the output current of an AQFP logic gate is too weak to drive more than one gate, splitter cells are needed to branch the output signals of multi-fanout gates. For an AQFP circuit, the total number of additional buffers and splitters may be much more than the number of logic gates, significantly impacting the circuit’s power, performance, and area. In this work, we propose several techniques to (i) reduce the total number of required buffers and splitters and (ii) perturb the levels of logic gates to seek more opportunities for optimization. Experimental results show that, compared to state-of-the-art methods, our approach can obtain optimized results with less additional inserted buffers/splitters in shorter run times, especially in larger circuits.