Abstract
In this paper, a bit-level systolic array with bit-serial arithmetic is proposed for inner product computation. If data vectors are entered continuously and interleavedly, the proposed inner product array can be fully utilized for one of two operating modes: 1) computing two independent inner products concurrently; 2) computing the sum of two inner products or an inner product with a double size. For a given data word length B, the system yields two outputs every 2B cycles for mode 1 (i.e., the average throughput is one per B cycles), and one output every 2B cycles for mode 2. As compared to existing related arrays, the proposed one has a little increase in hardware complexity, but is more flexible for use in applications. FIR filters based on the inner product array are given for demonstration of the flexibility. © 1991 Taylor and Francis Group, LLC.