摘要
The capability to detect small objects precisely in real time is essential for intelligent systems, particularly in advanced driver assistance systems (ADASs), as it ensures continuous awareness of distant obstacles for enhanced safety. However, achieving high detection precision for small objects requires high-resolution input inference on deep convolutional neural network (CNN) backbones combined with advanced multi-layer bi-directional feature pyramid networks (BiFPNs), which significantly increase memory and computation costs on conventional accelerators. This work presents a memory- and energy-efficient dedicated processor supporting high-resolution small-object detection. The chip integrates a flow-model co-optimized implementation for multi-layer BiFPN, leveraging orientation-interleaved causally-processed (OICP) modeling to simultaneously reduce off-chip and on-chip memory requirements. To reduce energy consumption in deep backbone inference with high-resolution inputs, we further optimize system dataflow and computation units for lightweight operations, such as depth-wise convolution (DWC) and channel attention (CA). Specifically, a memory-efficient scheduling scheme reduces external memory access (EMA) and SRAM usage via selective feature re-computation and bottleneck-shaped layer fusion (LF), while a reconfigurable tensor engine (RTE) enhances computation utilization across diverse operations. Dynamic power is further reduced by a low-toggle sign-magnitude-two's-complement (SMTC) processing element (PE) design. Fabricated in 16-nm FinFET technology, the proposed chip achieves an energy efficiency of 4.1-8.9 TOPS/W, enabling deployment across a wide range of scenarios, particularly in power-constrained devices. Operating at 480 MHz, it supports EfficientDet-D3-OICP and EfficientDet-D2-OICP inference at input resolutions of 896 × 896 and 768 × 768, achieving 26.6 and 50.3 fps, respectively. Leveraging the proposed techniques, the chip maintains an on-chip memory footprint comparable to or smaller than that of prior ASIC designs, while delivering at least a 19% improvement in detection precision of small objects, \mathrm \text mAP_(s), on the challenging COCO dataset.