摘要
This paper presents a hardware accelerator for extended Gaussian elimination (ExtGaussElim), targeting the WAVE post-quantum signature scheme. ExtGaussElim is the primary performance bottleneck in WAVE, and we propose three key contributions to improve its hardware implementation. First, we design a novel processing unit that minimizes the variety of operations required over the Galois Field GF(3), streamlining the Gaussian elimination process. Second, we develop a reconfigurable architecture that supports flexible performance scaling. Third, we introduce an optimized data memory layout to reduce the hardware resource footprint. The proposed ExtGaussElim accelerator is implemented and evaluated on the xc7a200t. To the best of our knowledge, this work presents the first hardware implementation of ExtGaussElim. The proposed ExtGaussElim accelerator is implemented and evaluated on the Digilent Arty Z7-10 FPGA board. To the best of our knowledge, this work presents the first hardware implementation of ExtGaussElim. Experimental results demonstrate a 6.25× speed-up over a CPU-based implementation and an over 100× speed-up without considering software data transformation, highlighting the significant performance advantage of the hardware accelerator.