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An efficient multimode multiplier supporting AES and fundamental operations of public-key cryptosystems
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An efficient multimode multiplier supporting AES and fundamental operations of public-key cryptosystems

Chen-Hsing Wang, Chieh-Lin ChuangCheng-Wen Wu
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 卷.18(4), 頁碼.553-563
04/2010

摘要

Advanced Encryption Standard (AES) Composite field arithmetic Digital signal algorithm (DSA) Elliptic-curve cryptography (ECC) Montgomery multiplication (MM) Rivest, Shamir, and Adleman (RSA) Software Hardware and Architecture Electrical and Electronic Engineering
This paper presents a highly efficient multimode multiplier supporting prime field, namely, polynomial field, and matrixvector multiplications based on an asymmetric word-based Montgomery multiplication (MM) algorithm. The proposed multimode 128 × 32 b multiplier provides throughput rates of 441 and 511 Mb/s for 256-b operands over GF(P) and GF(2 n ) at a clock rate of 100 MHz, respectively. With 21930 additional gates for Advanced Encryption Standard (AES), the multiplier is extended to provide 1.28-, 1.06-, and 0.91-Gb/s throughput rates for 128-, 192-, and 256-b keys, respectively. The comparison result shows that the proposed integration architecture outperforms others in terms of performance and efficiency for both AES and MM that is essential in most public-key cryptosystems. © 2006 IEEE.

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