Abstract
This study presents an ultra-low-power 24 GHz low-noise amplifier (LNA) using 0.13 μm CMOS technology. We propose of using the minimum noise measure (M MIN ) as the guideline to determine the optimal bias and geometry of the transistors in the circuit. The power-constrained simultaneous noise and input matching (PCSNIM) technique is also employed for this design. With the proposed design approach, the LNA achieves a peak gain of 9.2 dB and a minimum NF of 3.7 dB under a supply voltage of 1 V. The associated power consumption is only 2.78 mW. © 2010 IEEE.