摘要
In this paper, an automatic technique for test timing assignment is proposed which is comprehensive enough to take the test objective (e.g., strictness of selected AC timing parameters) and the constraints from both RAM specification and tester into consideration. Since test timing assignment problem could only be solved manually before, therefore, our work can significantly reduce the efforts and costs on developing and maintaining timing modules of RAM test programs. In the proposed technique, the test timing assignment problem is transformed into a linear programming (LP) model, which can be automatically solved. Examples of building LP models for an asynchronous DRAM are given to show feasibility of the proposed technique.