BIST-based diagnosis scheme for field programmable gate array interconnect delay faults

Y.-L. Peng; C.-W. Wu; J.-J. Liou; C.-T. Huang

doi:10.1049/iet-cdt:20060197

BIST-based diagnosis scheme for field programmable gate array interconnect delay faults

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BIST-based diagnosis scheme for field programmable gate array interconnect delay faults

Y.-L. Peng, C.-W. Wu, J.-J. Liou 和 C.-T. Huang

IET Computers and Digital Techniques, 卷.1(6), 頁碼.716-723

2007

DOI: https://doi.org/10.1049/iet-cdt:20060197

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Software

Hardware and Architecture

Electrical and Electronic Engineering

A new built-in self-test (BIST)-based diagnosis scheme for field programmable gate array (FPGA) interconnect delay faults is proposed. Faulty paths can be located after configuring the output response analyser of the BIST circuit as a scan chain. By analysing these faulty paths, segment fault candidates can be obtained. The proposed diagnosis scheme can find effective test paths to locate faulty segment candidates. Experimental results for an island-style FPGA show high diagnosis resolution in locating the faulty paths, under single- and double-fault models caused by single and double defects, respectively. © The Institution of Engineering and Technology 2007.

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題名: BIST-based diagnosis scheme for field programmable gate array interconnect delay faults
翻譯題名: BIST-based diagnosis scheme for field programmable gate array interconnect delay faults
創作者：: Y.-L. Peng (作者) - National Tsing Hua University
C.-W. Wu (作者) - National Tsing Hua University
J.-J. Liou (作者) - National Tsing Hua University
C.-T. Huang (作者) - Department of Electrical Engineering , National Tsing Hua University
學術資源類型: 期刊文章
出版日期: 2007
出版資訊: IET Computers and Digital Techniques, 卷.1(6), 頁碼.716-723
語言: 英語

BIST-based diagnosis scheme for field programmable gate array interconnect delay faults

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