摘要
A hybrid P/N channel junctionless (JL) thin-film transistor (TFT) with back-gate bias (V <sub>bg</sub> ) has been demonstrated. By applying negative bias of V <sub>bg</sub> = -8 V in gate length of 50 nm shows excellent SS (<90 mV/dec), a negligible drain induced barrier lowering (DIBL), increased I <sub>on</sub> versus decreased I <sub>off</sub> (ratio > 10 <sup>8</sup> ), and high V <sub>th</sub> modulation. The increased I <sub>on</sub> simultaneously decreased I <sub>off</sub> via negative V <sub>bg</sub> is attributed to smaller surface E-field at ON-state, significantly reducing the impact on interface traps and thinner effective channel thickness at OFF-state, improving gate controllability. Hence, hybrid P/N JL-TFT with V <sub>bg</sub> is a promising for low power circuit, power management, and System-on-Chip applications.