Bayesian decision analysis for optimizing in-line metrology and defect inspection strategy for sustainable semiconductor manufacturing and an empirical study

In-line metrology for defect inspection is employed for quality control and calibration of data-driven models for intelligent manufacturing. However, defect inspection is time-consuming that will prolong cycle time and increase production cost and energy consumption. The engineers in different workstations may skip more sampling lots for in-line metrology to save cycle time and enhance productivity. Owing to unsynchronized skipping lots along different fabrication stages, the unexpected quality loss may be caused occasionally. However, little research has been done on the present problem. To fill the gaps, this study aims to develop a decision framework for dynamically optimizing the defect inspection strategy and in-line metrology resource allocation including the sampling rate, the sampling period determination, and selecting specific defect inspection lots to enhance the information gain and coverage in high-mix wafer foundry subject to the risks for productivity and sustainability. An empirical case study was conducted in a leading semiconductor manufacturing company for validation. The results have shown practical viability of the developed solutions that have been employed for implementation.