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Breakdown voltage model and electrical characteristics of CMOS compatible RESURF STI drain extended MOS transistors
Journal article   Peer reviewed

Breakdown voltage model and electrical characteristics of CMOS compatible RESURF STI drain extended MOS transistors

Hung-Chih Tsai, Yogendra Yadav, Ruey-Hsin Liou, Kuo-Ming Wu, Yi-Chin Lin and Chenhsin Lien
IEEE Transactions on Electron Devices, Vol.62(6), pp.1958-1963
01/06/2015

Abstract

Drain extended MOS (DEMOS) Lateral doublediffused MOS (LDMOS) Reduced surface field (RESURF)
A CMOS compatible high-voltage shallow trench isolation (STI) drain extended MOS (DEMOS) transistor is fabricated and its electrical characteristics are studied. A local p-well (PW) plate served as a reduced surface field is adopted to enhance the breakdown voltage (BV) by reducing the effective doping concentration of the accumulation region. The conformal-mapping method is used to evaluate the BV of this 2-D STI DEMOS structure theoretically. A BV model, which relates the BV to the width of the accumulation region xa and the overlap/underlap Op between the local PW plate and the STI, is derived. The predictions of this model agree very well with both the experimental data and the technology computer-aided-design simulations. © 1963-2012 IEEE.

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