Abstract
This letter demonstrates a p-type raised source-and-drain (raised S/D) junctionless thin-film transistors (JL-TFTs) with a dual-gate structure. The raised S/D structure provides a high saturation current (>1 μA/μm). The subthreshold swing (SS) is 100 mV/decade and the drain-induced barrier lowering (DIBL) is 0.8 mV/V, and the I<inf>on</inf>/I<inf>off</inf> current ratio is over 10<sup>8</sup> A/A for L<inf>g</inf> = 1 μm. Using a thin channel structure obtains excellent performance in the raised S/D structure. Besides the basic electrical characteristics, the dual-gate structure can also be used to adjust V<inf>th</inf> in multi-V<inf>th</inf> circuit designs. This study examines the feasibility of using JL-TFTs in future three-dimensional (3D) layer-to-layer stacked high-density device applications.