Clock-Latency-Aware Fault-Tolerant DLL for Multi-Die Clock Synchronization

Yung-Chuan Su; Shi-Yu Huang

doi:10.1109/TCAD.2022.3226156

Clock-Latency-Aware Fault-Tolerant DLL for Multi-Die Clock Synchronization

期刊文章

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Clock-Latency-Aware Fault-Tolerant DLL for Multi-Die Clock Synchronization

Yung-Chuan Su 和 Shi-Yu Huang

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

2022

DOI: https://doi.org/10.1109/TCAD.2022.3226156

摘要

Delay-Locked Loop

Fault-Tolerant

Process Resilient

Soft Error

Timing Correction Scheme

Software

Computer Graphics and Computer-Aided Design

Electrical and Electronic Engineering

A Delay-Locked Loop (DLL) circuit is indispensable for clock synchronization in a chip incorporating several heterogeneous dice. It has been shown previously that a fault and soft-error tolerant DLL can be achieved by Triple-Module Redundancy (TMR) enhanced with a timing correction scheme. However, the prior work still has a severe limitation -it does not consider the latency of the clock tree, and this limitation will make it infeasible in realistic situations. We demonstrate in this paper that this limitation can be overcome by a new &null architecture, thereby making a fault and soft-error-tolerant DLL truly realistic.

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詳細資料

題名: Clock-Latency-Aware Fault-Tolerant DLL for Multi-Die Clock Synchronization
翻譯題名: Clock-Latency-Aware Fault-Tolerant DLL for Multi-Die Clock Synchronization
創作者：: Yung-Chuan Su (作者) - National Tsing Hua University
Shi-Yu Huang (作者) - Electrical Engineering Dept, National Tsing Hua University, Taiwan
著作權: IEEE
學術資源類型: 期刊文章
出版日期: 2022
出版資訊: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
語言: 英語

Clock-Latency-Aware Fault-Tolerant DLL for Multi-Die Clock Synchronization

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