Abstract
IP reuse methodology has been used extensively in SoC (system-on-chip) design. In this reuse methodology, while design and implementation costs are saved, manufacturing cost is not. To further reduce the cost, this reuse concept has been proposed at mask and die level in three-dimensional integrated circuits (3D-IC). In order to achieve manufacturing reuse, in this article, we propose a new methodology for designing a global clock tree in 3D-IC. The objective is to extend an existing clock tree in 2D IC to 3D IC, taking into consideration the wirelength, clock skew, and the number of TSVs. Compared with NNG- and 3D-MMM-based methods, our proposed method reduces the wirelength of the new die and the skew of the global 3D clock tree on average, 5.85% and 2.3%, and 76.92% and 48.7%, respectively. In more than two die design, the average improvements of the wirelength and clock skew of ourmethod as compared with the 3D-MMM-based method are 4.23% and 46.84%, respectively. © 2014 ACM.