摘要
Layout patterns, including salient gate width and dummy active diffusion region (dummy OD), significantly influence the carrier mobility gain of nano scale devices. Germanium (Ge)-based devices with Ge–tin (GeSn) alloy embedded in the source/drain (S/D) regions have been regarded a promising candidate for higher channel mobility. Second-order piezoresistance coefficients were used to estimate the carrier mobility gain within the desired Ge-based device channel. A 20 nm Ge-based p-type metal oxide semiconductor field effect transistor with 100 nm gate width and 100 nm dummy OD width was selected to explore the layout effect of the short channel device. The device consisted of S/D region Ge 1−x Sn x alloy, compressive-stressed contact etch stop layer, and deposited shallow trench isolation with different process-induced stress magnitudes. Maximum carrier mobility gain of 93.65% was obtained when a 10 nm narrow distance between OD and dummy OD was achieved.