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Configurable Cubical Redundancy Schemes for Channel-Based 3-D DRAM Yield Improvement
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Configurable Cubical Redundancy Schemes for Channel-Based 3-D DRAM Yield Improvement

Bing-Yang Lin, Wan-Ting Chiang, Cheng-Wen Wu, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng 和 Min-Jer Wang
IEEE Design and Test, 卷.33(2), 頁碼.30-39
04/2016
DOI: https://doi.org/10.1109/MDAT.2015.2455347

摘要

3D DRAM built-in self-repair (BISR) built-in self-test (BIST) memory testing redundancy analysis (RA) redundancy repair yield improvement Software Hardware and Architecture Electrical and Electronic Engineering
Three-dimensional stacked memory stacking logic and memory dies are one of the most promising 3-D integration applications. This paper proposes two memory redundancy schemes to improve the yield of channelbased 3-D stacked DRAM by sharing spare memory across dies and satisfying channel constraints at the same time. The proposed schemes achieve much higher yield with very small area overhead than other memory redundancy schemes.

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