Controller architecture for low-power, low-latency DRAM with built-in cache

Zhi-Yong Liu; Hsiu-Chuan Shih; Bing-Yang Lin; Cheng-Wen Wu

doi:10.1109/MDAT.2016.2524445

Controller architecture for low-power, low-latency DRAM with built-in cache

期刊文章

同儕審查

Controller architecture for low-power, low-latency DRAM with built-in cache

Zhi-Yong Liu, Hsiu-Chuan Shih, Bing-Yang Lin 和 Cheng-Wen Wu

IEEE Design and Test, 卷.34(2), 頁碼.69-78

04/2017

DOI: https://doi.org/10.1109/MDAT.2016.2524445

摘要

3D DRAM

built-in cache DRAM (BC-DRAM)

DRAM controller

memory hierarchy

tiered latency DRAM (TL-DRAM)

Software

Hardware and Architecture

Electrical and Electronic Engineering

Memory wall is a critical issue for many today's electronic systems. Tiered latency DRAM with asymmetric bit lines was proposed to optimize the power and latency. This paper proposes a controller architecture for the tiered latency DRAM in which the small array is operated like a cache. - Jin-Fu Li, National Central University

指標

1 檢視次數

詳細資料

題名: Controller architecture for low-power, low-latency DRAM with built-in cache
翻譯題名: Controller architecture for low-power, low-latency DRAM with built-in cache
創作者：: Zhi-Yong Liu (作者) - Department of Electrical Engineering , National Tsing Hua University
Hsiu-Chuan Shih (作者) - National Tsing Hua University
Bing-Yang Lin (作者) - National Tsing Hua University
Cheng-Wen Wu (作者) - Department of Electrical Engineering , National Tsing Hua University
學術資源類型: 期刊文章
出版日期: 04/2017
出版資訊: IEEE Design and Test, 卷.34(2), 頁碼.69-78
語言: 英語

Controller architecture for low-power, low-latency DRAM with built-in cache

摘要

相關連結

指標

詳細資料

National Tsing Hua University 社交媒體