Abstract
ZrTiO 4 crystallized in orthorhombic (o-) phase was stacked with an amorphous Yb 2 O 3 interfacial layer as the gate dielectric for Si-based p-MOSFETs. With thermal annealing after gate electrode, the gate stack with equivalent oxide thickness (EOT) of 0.82 nm achieves high dielectric quality by showing a low interface trap density (D it ) of 2.75 × 10 11 cm -2 eV -1 near the midgap and low oxide traps. Crystallization of ZrTiO 4 and post metal annealing are also proven to introduce very limited amount of metal induced gap states or interfacial dipole. The p-MOSFETs exhibit good sub-threshold swing of 75 mV/dec which is ascribed to the low D it value and small EOT. Owing to the Y 2 O 3 interfacial layer and smooth interface with Si substrate that, respectively, suppress phonon and surface roughness scattering, the p-MOSFETs also display high hole mobility of 49 cm 2 /V-s at 1 MV/cm. In addition, I on /I off ratio larger than 10 6 is also observed. From the reliability evaluation by negative bias temperature instability test, after stressing with an electric field of-10 MV/cm at 85 °C for 1000 s, satisfactory threshold voltage shift of 12 mV and sub-threshold swing degradation of 3% were obtained. With these promising characteristics, the Yb 2 O 3 /o-ZrTiO 4 gate stack holds the great potential for next-generation electronics.