摘要
Detection of delay faults in 3-D interconnects is crucial for building reliable 3-D ICs. This paper presents a test methodology based on a globalring structure with a variable output thresholding technique to detect delay faults in multipin 3-D interconnects in multidie 3-D ICs. The proposed test architecture with an enhanced clock period measurement circuit detects delay faults in multipin 3-D interconnects with an accuracy of 10 ps.