Abstract
This paper presents architecture design, FPGA implementation, and measurement results of a real-time signal processing circuit for WCDMA uplink baseband receiver. To enhance uplink signal-to-interference-plus-noise ratio (SINR) performance, a four-element antenna array and a four-finger Rake combiner are integrated in the proposed receiver. Moreover, a low-complexity beamforming architecture using a correlator-based beam searcher, a decision-directed carrier synchronization loop, and a matched-filter based channel estimator is also designed. Simulations are based on the standard Doppler-fading scalar channel models provided by 3GPP and an extension to vector channel models that specify angle of arrival for each path is also made for beamformer simulation. Simulation and hard-ware emulation results show that the proposed architecture meets the specified requirements. In addition, this architecture, with its correlator-based beamformer weights, achieves such performance improvement with relatively low hardware complexity.