摘要
Scaled tunnel field-effect transistors (TFETs) endure severe short-channel and short-drain effects caused by direct source-to-drain and body-to-drain tunneling. This study numerically examined a Si-based asymmetric junctionless TFET (AJ-TFET) architecture for suppressing coupled short-channel and short-drain effects in and improving the on-current switching of TFET devices for ultralow-voltage CMOS applications. The junctional drain/body facilitates the extending of the off-state tunnel barrier into the drain, enhancing robustness against short-channel and short-drain effects. The junctionless source/body can minimize lateral coupling and thus lead to efficient switching in a TFET, thus generating steep on-off switching swings. The results revealed that in contrast to conventional PIN-TFETs, the AJ-TFET evaluated in this study exhibited considerably lower swing levels and higher current levels. The voltage-scaled AJ-TFET retained excellent subthreshold behaviors and short-channel robustness, offering adequate on-current levels along with minimized leakage levels. Incorporating high-k gate dielectrics into the devices enabled extra on-current boosting and swing minimization, further extending the deep-swing, high-current operation region. Because of their excellent on-off switching and on-current enhancement, the extremely scaled AJ-TFET could operate adequately at low gate and drain voltages (0.3-0.5 V); therefore, they are promising candidates for use in ultralow-voltage energy-efficient applications. © 2022 IOP Publishing Ltd.