摘要
Phase-locked loop (PLL) techniques are widely utilized for synchronization and control of grid-connected power electronic systems for estimation of phase angle, frequency, and amplitude of the grid voltage. Recently, an advanced scheme called the three-phase enhanced PLL (3P-EPLL) has been proposed for estimating the grid voltage information. However, recent studies have shown that this 3P-EPLL cannot provide accurate estimations under adverse grid conditions, especially when the grid voltage is polluted with harmonics, dc offsets, and unbalance. This paper proposes an improved scheme of 3P-EPLL. A novel filtering technique called the multiple delayed signal cancelation (MDSC) is integrated into both the phase-angle estimation loop, and the amplitude estimation loop of the 3P-EPLL for eliminating periodic ripples due to harmonics and unbalance in the grid voltage. MDSC filters can indeed provide more flexibility to configure the lowest undesired harmonics, and can have less delay time in the digital implementations when compared with moving average filters and cascaded delayed signal cancelation filters. Thus, the fast response time of the filter is expected. To improve the dynamic performance of the 3P-EPLL, the proportional-integral-derivative controller is used instead of the conventional proportional-integral controller. Comprehensive analysis of the MDSC-based 3P-EPLL is investigated. Both simulations and experimental studies are conducted to validate the prompt dynamic performance of the proposed MDSC-based 3P-EPLL.