摘要
In this paper, we investigate the impact of fin-shape, dimension, and geometry of tapered FinFET with 5-nm node (N5) technology using TCAD simulation. Fixed gate length (L G ) of 9nm, spacer length (L SP ) of 7nm, and bottom fin-width (F WB ) of 6nm were used. The other parameters, such as top fin-width (F WT ) and fin-height (F H ) were modulated to see the impact on the electrical characteristic and physical behaviors of the device. The simulation results show that increasing F H can enhance the saturation current (I SAT ) effectively. However, the threshold voltage (V TH ) will suffer so much. In addition, a higher F H means that a larger aspect ratio, thus it is not easy to fabricate in the manufacturing process. On the other hand, the saturation current can be improved by widening F WB . Nevertheless, it may not be a good choice because a wider F WB lets a larger cross-section device area for epitaxy source and drain. Tuning F WT may be the best choice to have a current gain. Additional 1nm F WT can enhance approximately 30% of the saturation current. Moreover, the V TH has no significant impact and it is good for source-drain epitaxy. By careful control of F H and F WT , the device performance can be predicted very well. As the results, Moore's law still can work even in N5 CMOS technology.