摘要
The reduction of transient enhanced diffusion (TED) and suppression of short-channel effect (SCE) are very critical for the formation of ultra shallow junctions required for deep sub-micron devices. This article reports the nanoscale gate length of p-type metal-oxide-semiconductor field-effect transistor (pMOSFET) technology using 72 Ge/ 74 Ge germanium preamorphization implantation (Ge PAI) upon the (1 0 0)-oriented silicon substrates. It is demonstrated that the channeling can be eliminated by the formation of a Ge-implantation induced thin amorphous layer near the surface prior to boron implantation. Optimizing the amorphous layer thickness by controlling a high 72 Ge/ 74 Ge ratio, the device performance of pMOSFETs can be enhanced. In addition, the optimum conditions of Ge PAI would help the confinement of boron ions to avoid the channeling phenomenon. It is also found that the thin Ge PAI amorphous layer formed by a low 72 Ge/ 74 Ge ratio would cause the degradation of threshold voltage (V th ) roll-off characteristics, I on /I off ratio and the fluctuation of 62.14% in gain factor, as compared to that formed by a high 72 Ge/ 74 Ge ratio. It is attributed to a thinner Ge amorphous layer that has a weak ability to suppress the channeling tail of boron, as compared to a thicker Ge amorphous layer at the same implanted doses and acceleration energies among various 72 Ge/ 74 Ge ratios. © 2010 Elsevier Ltd. All rights reserved.