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Electrical characteristic enhancement of metal-oxide-semiconductor devices by incorporating HfON buffer layer at HfTaSiON/Si interface
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Electrical characteristic enhancement of metal-oxide-semiconductor devices by incorporating HfON buffer layer at HfTaSiON/Si interface

Chin-Lung Cheng, Kuei-Shu Chang-Liao, Hsin-Chun Chang and Tien-Ko Wang
Solid-State Electronics, Vol.50(6), pp.1024-1029
06/2006

Abstract

Buffer layer HfON HfTaSiON Interface trap density Metal-oxide-semiconductor Stress-induced leakage current (SILC) X-ray photoelectron spectroscopy (XPS)
In this work, the electrical characteristic enhancement of HfTaSiON-gated metal-oxide-semiconductor devices with an additional HfON buffer layer was investigated. By forming a proper thickness of HfON buffer layer at HfTaSiON/Si interface, thermal stability and electrical characteristic enhancement including EOT, hysteresis, interface trap density, stress-induced leakage current and stress-induced flatband voltage shift can be achieved. X-ray photoelectron spectroscopy (XPS) demonstrates that the atomic percentage of Si-O bonds in interfacial layer is increased by introducing HfON buffer layer at HfTaSiON/Si interface. X-ray diffraction (XRD) depicts that, while deposited on the HfON buffer layer, the HfTaSiON film shows a more significant crystalline retardation characteristic. © 2006 Elsevier Ltd. All rights reserved.

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