Abstract
With a Si substrate, the p-MOSFET formed on a thin Ge layer with the thermal SiON as the gate dielectric was electrically characterized in this letter. The desirable passivation of the Ge channel is evidenced by the interface trap density lower than 3.46 × 10 11 cm -2 · eV -1 . A 1.74 × higher peak hole mobility than that of the Si universal one is obtained by the Ge MOSFET due to the low interface trap density and the good Ge crystallinity. With the source/drain region mainly formed on the Si substrate, the Ge MOSFET also demonstrates the excellent junction leakage. Combining these promising electrical characteristics, the thermal SiON with the device structure holds the potential to be applied to high-performance Ge MOSFETs. © 2008 IEEE.