Abstract
A stacked Si-{3}hbox{N}-{4}/hbox{HfO} 2 charge-trapping (CT) layer was proposed to improve erase operation and retention for CT nonvolatile memory (NVM) devices. The improvement can be attributed to the smaller valence band offset of Si-{3}hbox{N} 4 to Si and the higher barrier for electron detrapping from HfO 2 to Si-{3}hbox{N} 4 . The programming and retention characteristics of CT NVM devices can be further enhanced by inserting Al-{2}hbox{O} 3 between Si-{3}hbox{N} 4 and HfO 2 as the CT layer. This is because most of the injecting charges are trapped at the Si-{3}hbox{N}-{4}/hbox{Al}-{2}hbox{O} 3 interface, and Al-{2}hbox{O} 3 also provides a high barrier for electron detrapping. © 2012 IEEE.