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Enhancement of two-bit performance of dual-pi-gate charge trapping layer flash memory
Journal article   Peer reviewed

Enhancement of two-bit performance of dual-pi-gate charge trapping layer flash memory

Min-Feng Hung, Yung-Chun Wu, Tsung-Ming Tsai, Jiang-Hung Chen and Yi-Ray Jhan
Applied Physics Express, Vol.5(12), 121801
12/2012

Abstract

This work demonstrates a dual-pi-gate TaN-Al 2 O 3 -Si 3 N 4 -SiO 2 -silicon (TANOS) flash memory with nanowires (NWs) channel. Simulation under modulated Fowler-Nordheim (MFN) tunneling indicates that the source-side tunneling oxide of the dual-gate (DG) TANOS NVM has an electric field larger than 6 MV/cm. A novel 2-bit operation of DG TANOS NVM can thus be performed by MFN programming and band-to-band tunnelinginduced hot-hole injection (BTBTHHI) erasing. Additionally, the DG TANOS memory shows better program/erase characteristics and clearer distinguishability than a single-gate (SG) device under 2-bit operation. In reliability results, the DG TANOS memory shows better retention and endurance than the SG device. © 2012 The Japan Society of Applied Physics.

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