摘要
Present work demonstrates the vertically double stacked nanosheet (NS) p-channel polycrystalline silicon (poly-Si) junctionless field-effect transistors (JL-FET) with tri-gate, omega-gate, and gate all around (GAA) structure. These structures offer more W eff per existing footprint and better parallel resistance, resulting in smaller total resistance. Also, the GAA stacked NS device shows superior electrical properties, including high Ion/Ioff ratio (> 10 8 ), steep subthreshold swing (SS) = 100 mV/dec, very low drain-induced-barrier-lowering (DIBL) = 0.127 mV/V and usually off at Vg = 0 V, owing to superior gate controllability. More, the 3D TCAD simulation has applied for analysis of physical characteristics of the proposed devices.